1. Field of the Invention
The present invention relates to transistors, transistor arrays and non-volatile semiconductor memories.
2. Description of the Background Art
In recent years, non-volatile semiconductor memories such as Ferro-electric Random Access Memory, EPROM (Erasable and Programmable Read Only Memory), EEPROM (Electrically Erasable and Programmable Read Only Memory) have attracted much attention. In the EPROM or EEPROM, data is stored by storing charge at the floating gate and detecting a change in the threshold voltage based on the presence/absence of charge by a control gate. Such EEPROM includes a flash EEPROM which erases data for the entire memory chip or erases data on the basis of each of arbitrary blocks formed by dividing a memory cell array.
The flash EEPROM has increasing applicabilities such as for a memory for storing programs or data in a mobile telephone or a mobile information terminal for its advantages including: (1) stored data is non-volatile, (2) power consumption is low, (3) data can be electrically rewritten (rewritten on board), (4) the cost is low.
Memory cells forming the flash EEPROM include split-gate or stacked-gate type memory cells.
In flash EEPROM with the stacked-gate type memory cells, if charge is excessively pulled out from the floating gate electrode at the time of erasing data, the channel region attains an on state even if a prescribed voltage (0 V, for example) to drive a memory cell into an off state is applied to the control gate electrode. As a result, the memory cell continuously attains an on state, which disables reading of stored data, in other words, so-called over-erasure is caused. In order to prevent the over-erasure, the procedure of erasure must be devised, the procedure of erasure should be controlled, for example, by a peripheral circuit of the memory device, or by an external circuit.
The split-gate type memory cell was developed to prevent such over-erasure experienced in the stacked-gate type memory cell.
A flash EEPROM using a split-gate type memory cell is disclosed by WO92/18980.
FIG. 15 is a cross sectional view of a conventional split-gate memory cell 201.
Split-gate type memory cell (split-gate type transistor) 201 includes a source region 203, a drain region 204, a channel region 205, a floating gate electrode 206, and a control gate electrode 207.
N type source region 203 and drain region 204 are formed on a P type monocrystalline silicon substrate 202. Floating gate electrode 206 is formed on channel region 205 between source region 203 and drain region 204 with a gate insulating film 208 interposed therebetween. Control gate electrode 207 is formed on floating gate electrode 206 with an insulating film 209 and a tunnel insulating film 210 interposed therebetween. Insulating films 209 and 210 are formed by means of LOCOS (Local Oxidation of Silicon). Insulating film 209 forms raised portions 206a at both corners on the upper part of floating gate electrode 206.
Herein, a part of control gate electrode 207 is disposed on channel region 205 with insulating films 208 and 210 interposed therebetween to form a select gate 211. Select gate 211, source region 203 and drain region 204 form a select transistor 212. More specifically, split-gate type memory cell 201 includes a series-connection of a transistor and select transistor 212 formed of gate electrodes 206 and 207 and regions 203 and 204.
FIG. 16A is a partial cross sectional view of a memory cell array 302 in a flash EEPROM 301 using split-gate type memory cell 201.
Memory cell array 302 includes a plurality of memory cells 201 formed on P-type monocrystalline silicon substrate 202.
Two memory cells 201 (hereinafter also separately referred to as xe2x80x9c201axe2x80x9d and xe2x80x9c201bxe2x80x9d) commonly use source region 203 for the purpose of reducing the area occupied by the memory cells on substrate 202, and floating gate electrode 206 and control gate 207 are disposed in an inverted manner to common source region 203.
FIG. 16B is a partial plan view of memory cell array 302. FIG. 16A is a cross sectional view taken along line Xxe2x80x94X in FIG. 16B.
A field insulating film 213 is formed on substrate 202, and isolates memory cells. Source region 203 is common to memory cells 201a and 201b provided the longitudinal direction of FIG. 16B. Control gate electrode 207 is common to memory cells 201a and 201b disposed in the longitudinal direction of FIG. 16B, and control gate 207 forms a word line. Each drain region 204 disposed in the transverse direction of FIG. 16B is connected to a bit line (not shown) through a bit line contact 214.
FIG. 17 shows a general configuration of flash EEPROM 301 using split-gate type memory cell 201.
Memory cell array 302 includes a plurality of memory cells 201 formed in a matrix. The control gate electrodes 207 of memory cells 201 arranged in the row-direction form common word lines WL1 to WLn. The drain regions 204 of memory cells 201 arranged in the column-direction are connected to common bit lines BL1 to BLn.
Memory cells-201b connected to odd-numbered word lines (WL1, WL3, . . . , WLm, . . . , WLnxe2x88x921) and memory cells 201a connected to even-numbered word lines (WL2, WL4, WLm+1, . . . , WLn) respectively commonly use source regions 203, and common source regions 203 form source lines RSL1, . . . , RSLm, . . . , RSLn. Each memory cell 201b connected to word line WLm and each memory cell 201a connected to word line WLm+1, for example, commonly use source region 203, and the common source region 203 forms source line RSLm. Source lines RSL1 to RSLn are connected to a common source line SL.
Word lines WL1 to WLn are connected to a row decoder 303, and bit lines BL1 to BLn are connected to a column decoder 304.
A row address and a column address externally specified are input to an address pin 305. The row address and column address are transferred to an address latch 307 from address pin 305. Among the addresses latched at address latch 307, the row address is transferred to row decoder 303 through an address buffer 306, and the column address is transferred to column decoder 304 through the address buffer 306.
Row decoder 303 selects one of word lines WL1 to WLn (WLm, for example) corresponding to the row address latched at address latch 307, and controls the potential of each of word lines WL1 to WLn according to each operation mode which will be described. More specifically, by controlling the potential of each of word lines WL1 to WLn, the potential of the control gate electrode 207 of each memory cell 201 is controlled.
Column decoder 304 selects one of bit lines BL1 to BLn (BLm, for example) corresponding to the column address latched at address latch 307, and controls the potential of each of bit lines BL1 to BLn corresponding to each operation mode. More specifically, by controlling the potential of each of bit lines BL1 to BLn, the potential of the drain region 204 of each memory cell 201 is controlled.
Common source line SL is connected to a source line bias circuit 312. Source line bias circuit 312 controls the potential of each of source lines RSL1 to RSLn through common source line SL according to each operation mode. More specifically, by controlling the potential of each of source lines RSL1 to RSLn, the potential of the source region 203 of each memory cell 201 is controlled.
Externally specified data is input to data pin 308. The data is transferred to column decoder 304 through an input buffer 309 from data pin 308. Column decoder 304 controls the potential of each of bit lines BL1 to BLn based on the data as will be described later.
Data read out from an arbitrary memory cell 201 is transferred to a sense amplifier 310 through column decoder 304 from a corresponding one of bit lines BL1 to BLn. Sense amplifier 310 is a current sense amplifier. Column decoder 304 connects a selected one of bit lines BL1 to BLn and sense amplifier 310. Data amplified by sense amplifier 310 is externally output through data pin 308 from an output buffer 311.
The operations of the above-described circuits (303 to 313) are controlled by a control core circuit 313.
Operation modes (writing, reading and erasure) of flash EEPROM 301 will be now described in conjunction with FIGS. 18A, 18B and 18C.
(a) Writing (FIG. 18A)
The drain region 204 of a selected memory cell 201 is grounded through a constant current source 310a provided in sense amplifier 310 and has its potential set at about 1.2 V. The potential of the drain region 204 of each memory cell 201 other than the selected memory cell 201 is set at 3 V.
The potential of the control gate electrode 207 of the selected memory cell 201 is set at 2 V. The potential of the control gate electrode 207 of each memory cell 201 other than the selected memory cell 201 is set at 0 V.
The potential of the source regions 203 of all the memory cells 201 is set at 12 V.
In memory cell 201, the threshold voltage Vth of select transistor 212 is at about 0.5 V. Therefore, in selected memory cell 201, electrons in drain region 204 move into channel region 205 in an inverted state. As a result, cell current is passed from source region 203 to drain region 204. Meanwhile, the potential of source region 203 is at 12V, and therefore coupling between source region 203 and floating gate electrode 206 through capacitance raises the potential of floating gate electrode 206 close to 12 V. Hence, a high electric field is generated between channel region 205 and floating gate electrode 206. Electrons in channel region 205 are accelerated to be hot electrons and injected to floating gate 206 as denoted by arrow A in FIG. 18(A). As a result, charge is stored at the floating gate 206 of the selected memory cell 201, and 1-bit data is written and stored.
The writing may be performed on the basis of a selected memory cell 201.
(b) Reading (FIG. 18B)
The potential of the drain region 204 of a selected memory cell 201 is set at 2 V. The potential of the drain region 204 of each memory cell 201 other than the selected memory cell 201 is set at 0 V.
The potential of the control gate electrode 207 of the selected memory cell 201 is set at 4 V. The potential of the control gate electrode 207 of each memory cell 201 other than the selected memory cell 201 is set at 0 V.
The potential of the source regions 203 of all the memory cells 201 is set at 0 V.
As will be described, no charge is stored at the floating gate electrode 206 of a memory cell 201 in an erased state. Meanwhile, charge is stored at the floating gate 206 of a memory cell 201 in a written state as described above. As a result, channel region 205 immediately under the floating electrode 206 of a memory cell 201 in an erased state is in an on state, and channel region 205 immediately under the floating gate electrode 206 of a memory cell 201 in a written state is in an off state. Therefore, when 4 V is applied to control gate electrode 207, cell current passed from drain region 204 to source region 203 is larger for memory cell 201 in the erased state than for memory cell 201 in the written state.
Difference in the level of cell current between memory cells 201 is detected by sense amplifier 310 to read out the value of data stored in memory cell 201. For example, in a reading, the value of data in memory cell 201 in an erased state is represented by xe2x80x9c1xe2x80x9d, and the value of data in memory cell 201 in a written state is represented by xe2x80x9c0xe2x80x9d. More specifically, each memory cell 201 stores either of two values, the data value xe2x80x9c1xe2x80x9d of the erased state and the data value xe2x80x9c0xe2x80x9d of the written state, and the data value may be read out.
(c) Erasure (FIG. 18C)
The potential of the drain region 204 of each memory cell 201 is set at 0 V.
The potential of the control gate electrode 207 of a selected memory cell 201 is set at 15 V. The potential of the control gate electrode 207 of each memory cell 201 other than the selected memory cell 201 is set at 0 V.
The source regions 203 of all the memory cells 201 is set to 0 V.
The capacitance between source region 203 and substrate 202 and floating gate 206 is far larger than the capacitance between control gate electrode 207 and floating gate 206. More specifically, floating gate electrode 206 strongly couples source region 203 and substrate 202. As a result, if control gate electrode 207 is at 15 V and drain region 204 is at 0 V, the potential of floating gate electrode 206 does not much change, and the potential difference between control gate electrode 207 and floating gate electrode 206 becomes large, which generates a high electric field between electrodes 207 and 206.
As a result, Fowler-Nordheim Tunnel Current (hereinafter xe2x80x9cFN tunnel currentxe2x80x9d) is passed, so that electrons in floating gate electrode 206 are pulled toward control gate electrode 207 as denoted by arrow B, and data stored in memory cell 201 is erased.
At the time, since raised portion 206a is formed at floating gate electrode 206, electrons in floating gate 206 are ejected from raised portion 206a toward control gate electrode 207. As a result, the movement of electrons may be easier, and electrons in floating gate electrode 206 may be efficiently pulled out.
Herein, the control gate electrodes 207 of memory cells 201 arranged in the row-direction form common word lines WL1 to WLn. The erasure is therefore performed to all the memory cells 201 connected to a selected word line WLn.
Note that by selecting a plurality of word lines WL1 to WLn at a time, data in all the memory cells 201 connected to the selected word lines may be erased. Such operation of erasing data on a block-basis by dividing memory cell array 302 into arbitrary blocks each for a plurality of set of word lines WL1 to WLn is called xe2x80x9cblock erasurexe2x80x9d.
Flash EEPROM 301 using split-gate type memory cell 201 as described above is provided with select transistor 212, and therefore individual memory cells 201 are capable of selecting themselves. More specifically, if electrons are excessively pulled out from floating gate electrode 206 at the time of data erasure, channel region 205 may be turned off by select gate 211. Therefore if over-erasure is generated, the on/off state of memory cell 201 may be controlled using select transistor 212, in other words the over-erasure is no longer a problem. More specifically, select transistor 212 provided in memory cell 201 may select an on/off state for the memory cell itself.
A method of manufacturing memory cell array 302 will be now described one step after another.
Step 1 (FIG. 19A): A field insulating film 213 (not shown) is formed on substrate 202 by means of LOCOS. A gate insulating film 208 of a silicon oxide film is formed by means of thermal oxidation at a part without field insulating film 213 (element region) on substrate 202. Then, a doped polysilicon film 215 to be floating gate electrode 206 is formed on gate insulating film 208. A silicon nitride film 216 is formed on the entire surface of doped polysilicon film 215 by means of LPCVD (Low Pressure Chemical Vapor Deposition). After applying photoresist on the entire surface of silicon nitride film 216, an etching mask 217 for forming floating gate electrode 206 is formed by means of a normal photolithography technique.
Step 2 (FIG. 19B): Silicon nitride film 216 is anisotropically etched using etching mask 217, followed by removal of etching mask 217. Using thus etched silicon nitride film 216 as an oxidation mask, doped polysilicon film 215 is oxidized by means of LOCOS to form an insulating film 209. At the time, an end of insulating film 209 comes into an end of silicon nitride film 216 to form a bird""s beak 209a. 
Step 3 (FIG. 19C): Silicon nitride film 216 is removed. Using insulating film 209 as a mask, doped polysilicon film 215 is anisotropically etched to form floating gate electrode 206. At the time, since bird""s beak 209a is formed at an end of insulating film 209, an upper edge of floating gate electrode 206 is sharpened along the shape of bird""s beak 209a to form raised portion 206a. 
Step 4 (FIG. 19D): A tunnel insulating film 210 of a silicon oxide film is formed on the entire surface of the device formed by the process up to the above step by means of thermal oxidation or LPCVD or by both. Then, insulating films 208 and 210, and insulating films 209 and 210 placed upon each other are integrated.
Step 5 (FIG. 19E): A doped polysilicon film 218 to be control gate electrode 207 is formed on the entire surface of the device formed by the process up to the above step.
Step 6 (FIG. 19F): After applying photoresist on the entire surface of the device formed by the process up to the above step, an etching mask 219 for forming control gate electrode 207 is formed using a normal photolithography technique.
Step 7 (FIG. 19G): Using etching mask 219, doped polysilicon film 218 is anisotropically etched to form control gate electrode 207, followed by removal of etching mask 219.
Step 8 (FIG. 19H): After applying photoresist on the entire surface of the device formed by the process up to the above step, a mask 220 for ion injection for forming source region 203 is formed by means of a normal photolithography technique. Then, source region 203 is formed by implanting phosphorous ions (P+) onto the surface of substrate 202 by means of normal ion implantation, followed by removal of mask 220.
At the time, mask 220 is formed to cover at least a part on substrate 202 to be drain region 204 and to be restricted on floating gate electrode 206. As a result, the position of source region 203 is defined by ends of floating gate electrode 206.
Step 9 (FIG. 19I): After applying photoresist on the entire surface of the device formed by the process up to the above step, a mask 221 for ion injection for forming drain region 204 is formed by means of a normal photolithography technique. Then, arsenic ions (As+) are implanted to the surface of substrate 202 by means of normal ion implantation.
At the time, mask 221 is formed to cover at least source region 203 and to be restricted on control gate electrode 207. As a result, the position of drain region 204 is defined by ends of control gate electrode 207 on the side of select gate 211.
Removing mask 221 for ion injection completes memory cell array 302.
Flash EEPROM 301 using split-gate type memory cells 201 is encountered with the following problems.
(1) Mis-registration of mask 219 for forming control gate electrode 207 causes variations in the writing characteristic of memory cells 201.
As shown in FIG. 20A, in step 6, if mask 219 for etching to form control gate electrode 207 is shifted in position relative to memory cells 201a and 201b, the shape of control gate electrode 207 formed in step 7 will be different among memory cells 201a and 201b. 
At the time of forming drain region 204 by means of ion implantation in step 9, the position of drain region 204 is defined by ends of control electrode 207 on the side of select gate 211.
Therefore, as shown in FIG. 20A, if mask 219 for etching is shifted in position, the lengths (channel lengths) L1 and L2 of channel regions 205 of memory cells 201a and 201b will be different. Note, however, that if mask 210 is shifted in position, its width will not change, and therefore control gate 207 has the same width if its shape is different. For example, if the position of mask 219 is shifted toward memory cell 201b, the channel length L2 of memory cell 201b is smaller than the channel length L1 of memory cell 201a. 
If channel lengths L1 and L2 are different, the resistance of channel regions 205 will be different, which causes difference in the values of cell current passed at the time of writing. More specifically, the longer the channel length, the larger the resistance of channel region 205, and the smaller the cell current passed at the time of writing. If there is a difference between cell current values passed at the time of writing, the frequency of generation of hot electrons will differ. As a result, the writing characteristics of memory cells 201a and 201b will be different.
(2) Down-sizing of memory cell 201 is impeded in order to prevent the problem (1).
In designing split-gate type memory cell 201, in view of the precision of overlapping dimension of gate electrodes 206, 207 in addition to the precision of width size of gate electrodes 206, 207, the positional relation between gate electrodes 206, 207 and regions 203 and 204 should be provided with enough margin. However, in recent down-sizing processing of semiconductor, when a thin line having a width of about 0.5 xcexcm is processed, the precision of processing line width size as small as about 0.05 xcexcm is available, while the precision of registration size available is only about in the range from 0.1 to 0.2 xcexcm. More specifically, in split-gate type memory cell 201, the low registration size precision of gate electrodes 206 and 207 prevents down-sizing.
(3) Difficulty of down-sizing a split-gate type memory cell compared to a stacked-gate type memory cell.
The widths of a floating gate electrode and a control gate electrode in a stacked-gate type memory cell are the same, and both gate electrodes are placed upon each other without being shifted from each other. In contrast, in a split-gate type memory cell 201, a part of control gate electrode 207 is placed on channel region 205 to form select gate 211. As a result, in split-gate type memory cell 201, the area occupied by elements on substrate 202 is larger than the stacked-gate type memory cell by the area of select gate 211. In other words, while the split-gate type memory cell is free from the problem of over-erasure, the memory cell is not suitable for high density integration for the above (2) and (3).
(4) The structure of memory cell array 302 using split-gate type memory cells 201 is complicated and takes more man-hours for the manufacture.
The present invention is directed to the above-described problems, and has the following objects.
It is one object of the invention to provide a transistor free from variations in the writing characteristic, less suffering from over-erasure, and permitting down-sizing.
Another object of the invention is to provide a transistor array using the above-described transistor.
Yet another object of the invention is to provide a non-volatile semiconductor memory using the above-described transistor as a memory cell.
A still further object of the invention is to provide a non-volatile semiconductor memory using the above-described transistor array as a memory cell array.
A transistor according to one aspect of the present invention includes a semiconductor substrate having a main surface, source and drain regions formed on the main surface of the semiconductor substrate and having a channel region interposed therebetween, two floating gate electrodes positioned apart from each other on the channel region, one common control gate electrode extending on the two floating gate electrodes. The coupling capacitance between a floating gate electrode and control gate electrode is set larger than the coupling capacitance between the floating gate electrode and the semiconductor substrate.
A transistor according to another aspect of the invention includes a semiconductor substrate having a main surface, first and second impurity regions to be source/drain regions positioned apart from each other on the main surface of the semiconductor substrate, a channel region positioned between the first and second impurity regions, a gate insulating film formed on the channel region, a first floating gate provided in the vicinity of the first impurity region on the gate insulating film, a second floating gate electrode provided in the vicinity of the second impurity region on the gate insulating film, and a common control gate electrode formed on the first and second floating gate electrodes with a tunnel insulating film interposed therebetween. The coupling capacitance between a floating gate electrode and the control gate electrode is set larger than the coupling capacitance between the floating gate electrode and the semiconductor substrate.
In one embodiment, a transistor has a symmetrical structure relative to a virtual line drawn in the middle between the first and second floating gate electrodes and perpendicular to the main surface of the semiconductor substrate.
In another embodiment, a part of the control gate electrode positioned between first and second floating gate electrodes is positioned along the channel region to form a select gate.
In one operation mode, with a depletion layer expanded from the second impurity region toward the first impurity region, cell current is passed from the second impurity region to the first impurity region, coupling between the control gate electrode and the first floating gate electrode through capacitance causes a high electric field between the channel region and the first floating gate electrode, so that electrons are accelerated to be hot electrons, which are injected to the first floating gate electrode to store charge at the first floating gate electrode and data corresponding to the charge is written and stored.
In another operation mode, the first impurity region is grounded through a constant current source, first voltage is applied to the second impurity region, second voltage at a level higher than the first voltage is applied to the control gate electrode, electrons in the first impurity region move to a channel region in an inverted state, with a depletion layer expanded from the second impurity region toward the first impurity region, cell current is passed from the second impurity region to the first impurity region, coupling between the control gate electrode and the first floating gate electrode through capacitance raises the potential of the first floating gate electrode, a high electric field is generated between the channel region and the first floating gate electrode, which accelerates the electrons to be hot electrons, which are then injected to the first floating gate electrode to store charge at the first floating gate electrode, and data corresponding to the charge is written and stored.
In yet another operation mode, with a depletion layer expanded from the second impurity region towards first impurity region, based on the value of cell current passed from the second impurity region to the first impurity region, the value of data stored at the first floating gate electrode is read out.
In a still further operation mode, with a depletion layer expanded from the second impurity region to the first impurity region, the channel region immediately under the first floating gate electrode in an erased state is in an on state, the channel region immediately under the first floating gate electrode in a written state is in an off state, cell current passed from the second impurity region to the first impurity region is larger for the first floating gate electrode in the erased state than in the written state, and therefore the value of data stored at the first floating gate electrode is read out based on the value of the cell current.
In a still further operation mode, third voltages applied to the second impurity region, fourth voltage lower than the level of the third voltage is applied to the first impurity region, fifth voltage is applied to the control gate, charge is not stored at the floating gate electrode in the erased state with a depletion layer expanding from the second impurity region to the first impurity region, charge is stored at the floating gate electrode in the written state, the channel region immediately under the first floating gate electrode in the erased state is in an on state, the channel region immediately under the first floating gate electrode in the written state is in an off state, cell current passed from the second impurity region to the first impurity region is larger for the first floating gate electrode in the erased state than in the written state, and therefore the value of data stored at the first floating gate electrode is read out based on the value of the cell current.
In a still further operation mode, electrons in the first and second floating gate electrodes are pulled out to the substrate side, and data stored in the first and second floating gate electrodes are erased.
In an additional operation mode, sixth voltage at a constant level is applied to the first and second impurity regions, seventh voltage lower than the level of the sixth voltage is applied to the control gate, the potentials of the first and second floating gate electrodes strongly coupling with the control gate do not change much from the seventh voltage, the potential difference between the first and second impurity regions and the first and second floating gate electrodes becomes large, which generates a high electric field between the first and second impurity regions and the first and second floating gate electrodes, Fowler-Nordheim tunnel current is passed, so that electrons in the first and second floating gate electrodes are pulled out to the side of the substrate, and data stored at the first and second floating gate electrodes are erased.
A transistor array according to one aspect of the invention includes a semiconductor substrate having a main surface, and a plurality of transistors arranged in a matrix on the main surface of the semiconductor substrate. The transistors each include source and drain regions formed on the main surface of the semiconductor substrate having a channel region interposed therebetween, two floating gate electrodes positioned apart from each other on the channel region, and one common control gate electrode extending on the two floating gate electrodes. The coupling capacitance between the floating gate electrode and the control gate electrode is set larger than the coupling capacitance between the floating gate electrode and the semiconductor substrate.
In one embodiment, the control gate electrodes of the transistors arranged in the row-direction form common word lines, and the source/drain regions of the transistors arranged in the column-direction form common bit lines.
In another embodiment, the source/drain regions of the transistors arranged in the row-direction are isolated from each other, and the source/drain regions of the transistors arranged in the column-direction each form an independent bit line for transistors arranged in the row-direction.
In yet another embodiment, the control gate electrodes of the transistors arranged in the row-direction form common word lines, the transistor array is divided into a plurality of cell blocks, the source/drain regions of the transistors arranged in the column-direction in each block form common bit lines, the source/drain regions of the transistors arranged in the row-direction in separate cell blocks are isolated from each other, and the source/drain regions of the transistors arranged in the column-direction in adjacent cell blocks are isolated from each other to form separate bit lines.
In a still further embodiment, the control gate electrodes of the transistors arranged in the row-direction form common word lines, the transistor array is divided into a plurality of cell blocks, the source/drain regions of the transistors arranged in the column-direction in each cell block form common local short bit lines, a global bit line is provided corresponding to each local short bit line, and each local short bit line and each global bit line in each cell block are connected through a switching element.
In an additional embodiment, the floating gate electrodes of the transistors connected to a common word line are arranged in series to form a circuit which is connected in parallel to a common bit line to constitute an AND-NOR type structure.
A non-volatile semiconductor memory according to one aspect of the invention uses the above-described transistor as a memory cell.
A non-volatile semiconductor memory according to the present invention uses the above-described transistor array as a memory cell array.
According to the present invention, a transistor, a transistor array and a non-volatile semiconductor memory in a simple structure, free from variations in the writing characteristic, less suffering from the problem of over-erasure, and permitting down-sizing can be provided.